The present invention relates to a semiconductor device and particularly to a semiconductor device capable of verifying whether user data includes an error or not.
Some semiconductor devices, such as Dynamic Random Access Memories (DRAMs), have a user data error correction function. Such a semiconductor device includes a separate memory area for storing error check and correction information (ECC), in addition to a memory area for storing user data. See Japanese patent Laid Open publication No. 2002-25299, for example. The above semiconductor device corrects user data read in a read operation based on error correction information, and outputs the corrected user data to the outside. When carrying out a write operation, the semiconductor device generates error correction information, based on externally input user data, and writes the user data and the error correction information respectively to corresponding memory areas.
The semiconductor device described in the publication No. 2002-25299 has a function of switching a refresh cycle chip by chip according to an error rate, thus reducing the error rate of each chip to a certain error rate or less. Japanese patent Laid Open publication No. 2001-250378 discloses a DRAM having an error correction function. Japanese patent Laid Open publication No. 2011-165243 discloses a DRAM that sets a variable refreshing cycle.